Hardware Resources

Atom SBC runs on 3 Watts, decompresses HD Video at  4.5

Dave  Illar runs a demonstration showing the incredible low power capabilities of the Atom SBC

Video, see it to believe it.

http://www.eurotech-inc.com/Video-Eurotech-Low-Power-Overview.asp

The low power Intel® Atom CPU is not just for laptops and MIDs- it
is beginning to be applied as the center of single board computers for
general industrial, medical and commercial applications. This has
increased the demand for operation under extended and industrial
temperature regimes either by up rating the commercial Atom
processor, or by using the new Atom XL CPU. For ten years the
Columbia, MD design center of Eurotech has up rated ARM and other
CPU architectures, and we compared uprating of the standard Atom
part to the Atom XL, which is rated for either extended temperature
(-20°C to +70°C) or Industrial Temperature (-40°C to +85°C). We
performed some thermal tests to verify extended temperature range
and to further discuss the design and manufacturing issues
associated with the industrial temperature rated x86 chips.

The Intel® Atom™ Processor, with multithreading and virtualization, delivers x86 performance, minimizes power consumption and heat dissipation, eliminating the need for fans or heatsink, and brings powerful new technology to battery operated, space constrained embedded applications. To take advantage of the all the benefits offered and migrate through numerous product options, designers must understand intricacies involved in hardware, software, and end delivery to select the right Intel® Atom™ Processor -based solution for their embedded devices.

Author: Manfred Schmitz, Technical Director of MEN Mikro Elektronik

Both PICMG 2.30 – the rear I/O definition of CompactPCI – and the extension of CompactPCI standard CPLUS.0 are based on a star topology.

CompactPCI still uses the parallel PCI bus for communication between the system and peripheral boards. The maximum transmission speed of a parallel bus, however, is limited. Every additional board needs to share the bandwidth with the other bus participants. Also, the boards influence each other. Each one of the up to eight participants increases the electrical load on the bus, also reducing the theoretical maximum bandwidth of 33 MHz/32 bits with a peak data rate of 132 MB/s. If you increase the bus frequency to 133 MHz/64 bits (PCI-X), the maximum data rate goes up to 1 GB/s with only two possible participants – which is already a point-to-point connection with many lines.

Modern architectures are no longer busses but point-to-point connections. Their electrical characteristics are easier to manage and they permit higher data transmission rates with less pins. With just one link (i.e. one differential receive and one transmit line), PCI Express already achieves 250 MB/s. The bandwidth of this connection is not restricted by other bus participants. There is no direct influence. A higher number of links for a connection or a higher clock frequency further increase the data rate (up to 16 GB/s with Gen3) – and all this with full duplex.

Classic computers such as PCs have a hierarchical structure. At its "center" there is the computer that is surrounded by peripherals like the points of a star. This is independent of how the peripherals are controlled: via PCI Express, USB or SATA. Ethernet is an exception – you can read more on this in the next issue. If you project this architecture to modular computers like CompactPCI, there are a few technical challenges for the system slot and the backplane. Because of the star topology, the system slot must now provide a large number of connections. The backplane must spread all of these connections to the peripheral slots without needing too many layers. In the end, the price of modular computers must be able to compete with classic standard solutions. Standards like µTCA have defined switched fabric slots for this reason. These route the data over special backplanes as desired.

CompactPCI Plus intentionally does without such mechanisms. Its architecture does not need switches. The system slot is the center of the star. Each peripheral board is a symmetrical point. This is inexpensive and simple but assumes suitable connectors – which are now also available in rugged designs.

Author: By Eelco van der Wal, Chairman PICMG Europe

Introduction PICMG

Founded in 1994, PICMG's original mission was to extend the PCI standard, from the PCI Special Interest Group for use in non-traditional computer markets such as Industrial Automation, Medical, Military and Telecom. With the advent of fabric based transports, PICMG specs have continued to evolve. This has resulted in a series of specifications that include CompactPCI, AdvancedTCA, AdvancedMC, CompactPCI Express, COM Express and SHB Express.

Writing specifications is only the first step. Implementing is the next step. And for this a wide community is needed, ranging from connector suppliers, backplane suppliers, racks, power supplies, and yes – computer modules like processing and I/O. Together with its members PICMG creates eco systems to support the acceptance of the specifications as well as the multiple sources of supply.

Creating ecosystems as basis for the acceptance

In these days computer architectures like the serial CompactPCI Plus are complex. Because of this a multitude of different technologies comes together to standardize the architecture. Starting with the connector technology including simulation on the high speed data transfers, the next step is backplane technology with further simulation and real life measurements. And if these signals also can be delivered in the different topologies needed. Then the requirements on the power supply units come in. And racks, combined with cooling.

So even without the different suppliers for the computer modules itself, one needs already around 10 different suppliers to create an ecosystem at this level.

So in order to make a computer bus specification to become available and accepted in the market, one needs at least 20 suppliers supporting it and providing products ranging from connectors via racks to modules. This is what is often called an eco-system, supporting the market to accept an open standard.

One of the major benefits of such an open eco-system is that it provides extensive knowledge and experience on a broader scale then many in-house developments can ever build upon. And this broad and extensive knowledge is a pre requisite to provide state-of-the-art technologies like CompactPCI Plus to the open marketplace.

Authors:

Ben Paagman, Senior Project Engineer, FCI Netherlands

Marco Pagnin, FAE, FCI Germany            

FCI’s AirMax VSTM connector system is the currently proposed connector system as the backplane interface for Compact PCI Plus (CPlus.0). AirMax VS™ is a shieldless High Speed connector system with pressfit technology.

The IMLAs accumulate the contact columns which are insulated from each other by air gaining the highest speed dielectric. (AirMax).

For CPCI+ a version was chosen with four signal pairs per column. As the amount of pairs gives the height of the connector, this is the ideal configuration to maintain the mechanical compatibility to the IEEE 1101.

Another requirement for this application was to get 184 signal pairs (552 single contacts) into 95mm linear card edge, including coding to prevent plugging CPCI+ cards into common CPCI slots. Also it was decided by the PICMG to mount the receptacle part onto the backplane to prevent terminal stubbing on the backplane when card guiding is not optimal.

The AirMax VSTM connectors consists of single insert moulded leadframe assemblies, called IMLAs, which are mounted at a pitch of 2mm in a plastic front housing and a plastic retainer on the back side.

To protect the terminals of the header, AirMax VSTM is available with different wall configurations. Combining headers with a different wall count and a customized version with three walls, the headers are protected from all sides and to offering coding and guiding. On the outer left side the header with the four walls and six IMLAs is placed ( P1 connector), aside the headers with two walls an eight IMLAs side by side and on the outer right side the header with three walls and eight IMLAs (P6 connector). The related receptacles are mounted onto the backplane.

As CPCI+ should also support next generation bus standards, like SATA3.0, PCIe2.0, USB3.0, etc, the backplane connectors must show excellent high speed performance at 10Gbit/s and more. Insertion Loss is less than 0,6 dB @ 10Gb/s and the worse case Crosstalk is less then 3% @ 50ps signal rise-time ( 10-90%)

Also the current carrying capacity is an important issue, as a minimum of 60W rating per card has to be supplied. Airmax VS™ is able to deliver this power with 6 terminals without a temperature rise of more than 30 ºC. 

A further requirement was the realisation of mezzanine applications on the plug-in boards. (Ethernet options).

Rear I/O applications, direct into the backplane and midplane are both possible to realize with AirMax VSTM

Author: Roland Nuiten and Tilo Remhof; 3M™ Deutschland GmbH

Using modern high speed serial bus protocols, many System design engineers are looking for a boost in system performance. 2 mm hard-metric connector based designs have historically been unable to maximize performance and signal integrity due to severe crosstalk occurring at speeds greater than 1 Gbps.

3M’s new Ultra Hard Metric Connector is the industry’s first fully-shielded, lowest crosstalk 2mm Hard Metric connector. It can improve and enable the performance of 2mm Hard Metric systems without costly backplane redesigns or forklift upgrades.

The UHM socket connector is designed to be intermateable to 2 mm hard-metric (IEC 61076-4-101) headers and compatible with 2 mm hard metric PCB footprints. It therefore helps enable much greater performance in legacy backplane designs. As a result, standard Compact PCI and VME 64x systems can support a high density multi-gigabit, high-speed serial IO protocols such as SAS, SATA, Rapid IO, PCI Express and Gigabit Ethernet.

The patented “virtual coaxial box” shielding technology from 3M dramatically reduces the severe crosstalk commonly experienced at 1- to 1.5-Gbps speeds, allowing the new Ultra Hard Metric (UHM) socket connector from 3M to achieve speeds greater than 7 Gbps even when mated with standard unshielded 2 mm hard-metric headers.

The “virtual coaxial box” provides a matched impedance signal path and gives the designer the freedom to drive 100 Ohm differential signal pairs in both columns and rows. This provides maximum signal density and performance, but also maintains compatibility to common column-differential pair configurations found in legacy HM-systems and cable applications. 

As an example, the crosstalk is evaluated for a HM-HM mated pair and HM-UHM mated pair with 2 neighbouring aggressor pairs. In the tested environment, even at 7Gb/s, the UHM maintains its excellent shielding properties and reduces crosstalk significantly.

The modular design of the UHM socket connector from 3M also gives system design engineers the flexibility to design the right level of signal integrity while satisfying required mechanical constraints. Five-row (A, B, CL, CR, AB) and eight- row (D, E, DE, FL, FR) form factors are available for high signal density. In addition, the socket supports 100 ohm differential pairs in rows or columns. 

The new UHM socket connector from 3M is ideal for backplane applications using 2 mm hard-metric connector technology that require higher signal speeds combined with higher signal densities, such as VME bus (VME 64x) and CompactPCI backplane applications including test and measurement (PXI), process control, military, enterprise computing, telecommunications and factory automation.

Author: Andreas Lenkisch, Principal Engineer Backplanes at Schroff GmbH, Straubenhardt, Germany

Hybrid backplanes for CompactPCI Plus from stock

PICMG 2.30 is an extension of the CompactPCI specification PICMG 2.0 and is currently undergoing a round of voting by PICMG.

CompactPCI PlusIO extends CompactPCI with the aim of providing a soft migration path to the CompactPCI Plus (PICMG Cplus.0) specification, which is now based solely on serial protocols.

The modern serial interfaces such as PCI Express, SATA, USB and Ethernet that are lacking on CompactPCI are provided by a CompactPCI PlusIO (PICMG 2.30) CPU on the user-defined pins of the P2 connector of a 32-bit CPU board. From here a hybrid backplane designed to CompactPCI PlusIO (PICMG 2.30) connects these signals to peripheral CompactPCI Plus slots.

The P2 connector of the CPU board is compatible with its predecessor from the hard-metric series. This allows the CompactPCI PlusIO CPU both to be used in earlier 32-bit CompactPCI systems and to support new CompactPCI Plus systems.

System manufacturers participating in the specification process will offer a number of typical configurations as standard backplanes or standard systems as stock items. For certain applications further configurations are certain to become standard products in order to also create a basis for small projects. The next step will be to define 'pure' CompactPCI Plus backplanes and systems.

The illustrations show the existing configurations and those planned for the near future.

• a hybrid backplane with 4 CompactPCI and 4 peripheral CompactPCI Plus slots
• a hybrid backplane with 3 CompactPCI and 2 peripheral CompactPCI Plus slots plus a slot for a CompactPCI PSU (to PICMG 2.11 with "P47" connector)
• a pure CompactPCI Plus backplane with 9 slots and
• a pure CompactPCI Plus backplane with approx. 3-5 slots (still at planning stage)

Dual CPUs with sideboard or mezzanine expansion module for CompactPCI Plus, that support the old parallel bus and also the new architecture on separate slots, do not require special backplanes. Off-the-shelf single CPCI and Cplus backplanes may be combined in any required configuration, with any combination of slots. Left: a backplane can be configured with 1 to 8 CompactPCI slots; right: a CompactPCI Plus-compatible backplane with 1 to 9 slots. Power backplanes with 1 to 4 slots allow the configuration to be rounded down for small quantities. For projects requiring larger quantities, however, it will be economically more effective to design a special monolithic backplane to the project's exact requirements.

Author: Manfred Schmitz, Technical Director of MEN Mikro Elektronik

PICMG 2.30 is an extension of the CompactPCI® standard PICMG 2.0 and is available as a draft at present. The CompactPCI® specification permits to lead user I/O to the backplane via 3U boards on the 32-bit system slot. These signals are often used to provide the modern serial buses like PCI Express, SATA, USB and Ethernet. Until now no standard existed, which led to incompatibilities between the boards of different manufacturers. This is particularly detrimental if rear I/O signals like PCI Express are used directly to build hybrid backplanes for CompactPCI Express.

CompactPCI Plus IO – PICMG 2.30 – remedies this. It defines the pin assignment for four PCI Express links, four USB interfaces, four SATA interfaces and two Ethernet channels. In order to ensure electrical functionality a completely new but 100% compatible connector by 3M has been introduced as J2 connector. It is equipped with an additional internal shield so that it is able to support the required high freqencies even without additional ground pins.

The pin assignment has been chosen in such a way that a 32-bit PICMG 2.30 board can function in a 64-bit backplane. However, the rear I/O pins cannot be used in that case, because the pins are needed for the 64-bit extension. 64-bit PCI transmissions are not possible. In order not to lose all degrees of freedom, PICMG 2.30 still allows the usage of free pins for user-defined I/O. If you require only one Ethernet interface on the backplane and want to lead LVDS to the back for controlling a monitor, you can use the free pins of the second Ethernet interface for LVDS. The assignment has to be chosen in such a way though that an Ethernet device which might be connected to LVDS cannot be damaged.

CompactPCI PlusIO - PICMG 2.30 - is a 100%-compatible extension of PICMG 2.0, which fits modern chip technology and enables the migration to new standards like CompactPCI Plus. Future CPU boards should be developed with regard to PICMG 2.30 compatibility. This ensures that boards of different manufacturers are inter-exchangeable and guarantees compatibility to following standards like CompactPCI Plus.

Webinar | Multicore Meets AdvancedTCA: Maximize Your Return

• When: Tuesday, September 22, 2009
• Host: OpenSystems Media
• Time: 11:00 a.m. PST/ 2:00 p.m. EST/ 7:00 p.m. London
• Featured speaker: Jason Byrne, Senior Product Line Manager, Continuous Computing
• Sponsor: Continuous Computing
• Registration: https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=158931&sessionid=1&key=F8D72FBFF5618EF0329D3A2E5955E433&partnerref=cont&sourcepage=register

Event Description

An article by Nitin Tomar, Product Line Manager, Continuous Computing

The mobile industry is looking to tiered service offerings to strengthen Average Revenue per User (ARPU), A preintegrated AdvancedTCA-based DPI module, as Nitin explains, can play a role here as 3G to LTE migration ensues.

Network operators worldwide are gearing up to provide 100 Mbps downlink and 50 Mbps uplink speed to mobile users with Long Term Evolution (LTE) technology. With LTE, users can expect to experience bandwidth that is three to four times the current downlink levels for High Speed Downlink Packet Access (HSDPA) and two to three times the current High Speed Uplink Packet Access (HSUPA) levels. Having gone through evolutions from GSM, EDGE, GPRS, and 3G in the last 15 to 20 years, one thing that the telecommunications industry has learned time and again is that the traditional approach of migrating a core network to a new technology is similar to undergoing a painful surgery.

New networks have been rolled out in a green field manner, thus making the transition capital intensive, time consuming, and often prone to errors. Delays encountered during the rollout due to interoperability issues, difficulties with new platforms, and so on have cost both network operators and equipment manufacturers significant revenue. Network operators end up being consumed in focusing almost exclusively on the “working rollout,” and they have missed the opportunities to add value differentiation during the upgrade to new technologies.

Fortunately, wireless operators’ core network migration from 3G to LTE will not be nearly as painful as earlier transitions. Thanks to AdvancedTCA standards-based LTE solution blades offering Deep Packet Inspection (DPI) features, combined with simplified LTE network architecture, operators will be able to capture the value differentiation offered by Commercial Off The Shelf (COTS) solution blades specifically designed for LTE networks.

3GPP’s LTE network consists of the Evolved Packet Core (EPC) and Evolved UMTS Terrestrial Radio Access (E-UTRA). LTE’s promise at the EPC is a simplified and flat “All IP” core network which consists of the Mobility Management Entity (MME), Serving Gateway (SGW), and Packet Data Network Gateway (PDN Gateway, or PGW). On E-UTRA, LTE offers less complexity by supporting flexible carrier bandwidths. Figure 1 compares 3G and LTE networks. In LTE, the combination of the EPC and Evolved UMTS is called the Evolved Packet System (EPS).

Much more of this article is available on: http://www.ccpu.com/news/articles/200905-ATCAforLTE.html

The FlexCompute ATCA-XE60 is a dual socket single board compute blade supporting 8 cores / 16 threads via two high performance Intel Xeon 5500 series "Nehalem" processors. The XE60 provides support for 4 hard drives, 64GB memory, and an optional RTM with additional network interface options. It is ideal for DPI, LTE wireless infrastructure (e.g., MME / SGW), and IPTV and edge storage applications.

The XE60 was designed with performance in mind, supporting the option of either the Intel Xeon L5518 or the higher power Intel Xeon E5540 processor. The blade can address low entry points via a single CPU option and scale to two processors without the need for full re-qualification.

Featuring over 1 terabyte of storage, the XE60 has two low-cost solid state disks on the main blade and an additional two drives on the RTM with RAID support. The RTM also supports a high performance 4-port external SAS connector as well as up to 32GB of cost-effective USB Flash.

The XE60 features two mezzanine sites for the addition of offload engines (e.g., encryption co-processor for Snow3G) and a dual 10G fabric NIC supporting iSCSI, TCP offload, VLAN tagging, and congestion control. Since the blade has been validated with leading hypervisors, it is an ideal platform because support for extended VT-x and VT-d decreases the overhead associated with virtualization.

The XE60's superior architecture not only doubles the performance of previous generation compute blades but also lays the foundation for future advances. In particular, the XE60 offers native support for the next generation Intel Xeon 6-core processor (codenamed "Westmere") which is expected to provide pin-compatible performance improvements of up to 50%.

The XE60 is built on industry standards to ensure easy integration and management for faster time-to-market development. Coupled with Continuous Computing's FlexPacket ATCA-PP50, FlexCore ATCA-FM40, optimized Trillium control and data plane protocol software, and professional services, the XE60 ATCA dual Nehalem quad-core completes the company's industry-leading 10GbE family of ATCA platform solutions. From IPTV servers to session border controllers, the XE60 is the blade of choice for deploying a wide range of high-performance, scalable telecom applications.

For more information see: http://www.ccpu.com/products/atca/xe60dualnehalem.html

The FlexCompute ATCA-XE50 completes Continuous Computing's 10GbE product offering. As the first AdvancedTCA (ATCA) Intel quad-core processor compute blade on the market, the XE50 is the ideal high performance ATCA compute blade which is optimized for telecom equipment manufacturers seeking superior Intel-based processing power. The XE50 provides the flexibility for customizing 10GbE-based systems that power the delivery of video and data content in IPTV networks, security, wireless core, and IP Multimedia Subsystem (IMS)-based broadband solutions.

The XE50's best-in-class performance is driven by two Quad-Core Intel® Xeon® processors designed with up to 24GB of memory (48GB future), an AdvancedMC slot, and multiple storage options for flexibility. The XE50 is designed as a modular processor blade with 12MB of L2 cache, single & dual processor configurations, and support for multiple operating systems. Additional connectivity is accomplished with a Rear Transition Module featuring multiple USB and GbE and hard drive options.

The XE50 is built on industry standards to ensure easy integration and management for faster time-to-market development. Coupled with Continuous Computing's FlexPacket ATCA-PP50, FlexCore ATCA-FM40, optimized Trillium control and data plane protocol software, and integrated professional services, the XE50 completes the company's industry-leading 10GbE family of ATCA platform solutions. From IPTV servers to session border controllers, the XE50 is the blade of choice for deploying a wide range of high-performance, scalable telecom applications.

For more information, please see http://www.ccpu.com/products/atca/xe50.html

Author: Andreas Lenkisch, Principal Engineer Backplanes at Schroff GmbH, Straubenhardt, Germany

CompactPCI Plus is a new standardisation project by the PCI Industrial Manufacturers Group (PICMG) that defines a successor architecture for the CompactPCI bus.

The principal features of this project are:

•  the introduction of the serial interface currently provided by chipsets, such as PCIe, USB, SATA and Ethernet,
• the development of a low-cost architecture that will also give former IPC users access to this robust and modular world,
•  the creation of a flexible architecture that provides the appropriate infrastructure for a wide range of application situations without high cost overheads, and
• the retaining of the CompactPCI ecosystem by creating a soft migration path from CompactPCI to CompactPCI Plus.

CompactPCI Plus naturally also supports rear I/O.

The peripheral CompactPCI Plus slot now requires only a small connector with 6 rows of contacts for power and signals. The remainder of the single-height euroboard remains free for user-defined I/O and offers 128 differential contact pairs or 384 contacts in total. This is significantly more than in 32-bit CompactPCI.

In 6U systems with double-height euroboards the entire upper section of the euroboard remains, as with CompactPCI, available for user-defined I/O. The new solution however features some substantial advantages.

While in CompactPCI both boards, front and rear, were linked via the backplane, in the new architecture both boards are inserted directly into one another. This does away with both a multilayered backplane in the I/O area and also the transfer connector onto it. Not only does this reduce costs; it also makes the system more flexible. There is no prescribed connector; this can be selected freely to suit economic and technical requirements.

In mechanical terms everything remains as previously; as before, the large building blocks of 19" technology can be used.

Ten ways a properly engineered Atom solution can give you advantage-

The extended-temperature Ocracoke Island SBC – based on the EP80579 Integrated Processor with Intel QuickAssist Technology – is ideal for low-cost wireless gateways, IP telephony platforms, and security appliances. See more on ADI's Open IP licensing and manufacturing model for standard and semi-custom designs and a series of SBC offerings based on Intel’s ground-breaking system-on-chip (SOC).

        Ocracoke Island SBC

        EP80579 Integrated Processor with Intel QuickAssist Technology

Author: Andreas Lenkisch, Principal Engineer Backplanes at Schroff GmbH, Straubenhardt, Germany

CompactPCI Plus is a new standardisation project by the PCI Industrial Manufacturers Group (PICMG) that defines a successor architecture for the CompactPCI bus.

The principal features of this project are:

• The introduction of the serial interface currently provided by chipsets, such as PCIe, USB, SATA and Ethernet,
• The development of a low-cost architecture that will also give former IPC users access to this robust and modular world,
• The creation of a flexible architecture that provides the appropriate infrastructure for a wide range of application situations without high cost overheads, and
• The retaining of the CompactPCI ecosystem by creating a soft migration path from CompactPCI to CompactPCI Plus.

CompactPCI Plus naturally also supports rear I/O.

The peripheral CompactPCI Plus slot now requires only a small connector with 6 rows of contacts for power and signals. The remainder of the single-height euroboard remains free for user-defined I/O and offers 128 differential contact pairs or 384 contacts in total. This is significantly more than in 32-bit CompactPCI.

In 6U systems with double-height euroboards the entire upper section of the euroboard remains, as with CompactPCI, available for user-defined I/O. The new solution however features some substantial advantages.

While in CompactPCI both boards, front and rear, were linked via the backplane, in the new architecture both boards are inserted directly into one another. This does away with both a multilayered backplane in the I/O area and also the transfer connector onto it. Not only does this reduce costs; it also makes the system more flexible. There is no prescribed connector; this can be selected freely to suit economic and technical requirements.

In mechanical terms everything remains as previously; as before, the large building blocks of 19" technology can be used.

Despite the plunge in the global economy, the digital signage market remains on an upward trend for the past three years. One the major reasons is that the technology of both software and hardware in DS become mature and applicable. NEXCOM is one of a handful experienced IPC companies dedicated to PC-based digital signage platforms. NEXCOM is proud to apply its solid experience in providing industrial-grade and high-performance digital signage solutions.

NEXCOM has created a full range of digital signage platforms. The PDS 5120-A, powered by Intel® Atom™ N270 processor, has an inbuilt HD decoder enabling it to simultaneously play full HD video, flash and scrolling text. In addition, the fan-less design appliance is made for ultra-reliable long-term operation. The PDS 5163, driven by Intel® Core™  2 Core with GM45 chipset, can output dual independent video with multi-zone contents in full HD mode.

Both above models support real-time content synchronization and absolutely easy to design  media layout for various applications. For more infomation please visit www.nexcom.com

The attached resource outlines the advantages of Lanner's Intel 5500 series platforms. Lanner';s platforms scale from single to quad CPU platforms with innovative network plugin cards to deliver high-band width computing platforms for network applications.

Should you have any questions about Lanner's platforms, contact Jesse Chiang at sales@lannerinc.com